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The future of 1553 is in IP cores. Click here to learn why.

MIL-STD-1553 BC Front End FPGA Core

MIL-STD-1553B Notice 2 Bus Controller front end Core for FPGA Devices

The BC1553FE FPGA core provides a simple to use link for CPUs that need to gain control over the MIL-STD-1553B Notice 2 bus.

The BC1553FE is typically used when a CPU needs to control a MIL-STD-1553 bus and is tightly synchronized with the 1553 transactions. BC1553FE works on a message level. All command words and data words are fed into the core, and the core responds with the returned data words and statuses of the Remote Terminals. The core is designed to work with two FIFOs, one for the words transmitted and one for the words received. The CPU has to manage these FIFOs from the other end.

Feature Summary:

MIL-STD-1553B Notice 2 Bus Controller (BC).
Suitable for any MIL-STD-1553 Bus Controller implementation.
Very simple FIFO interface to backend.
Best gate count in the industry (less than 900 4-LUT space).
Synthesis-able into any FPGA family.
Supports any whole number clock frequency.
Connects to any transceiver-transformer pair.
Vendor and technology independent IEEE-1076 VHDL design and coding.

Back End Interface

The BC1553FE is designed to interfaces CPU or user logic with elastic buffers such as FIFOs. The interface is on a message-by-message basis, there is no frame or minor frame mechanism, and thus the CPU should be handling that level of communication.

Gate Count

Vendor Family Used logic

Altera Cyclone 823 LEs

Altera Stratix 820 LEs

Xilinx Spartan2E 490 Slices

Xilinx Virtex II 487 Slices

Manchester Decoder

The unique Manchester decoder can work with any whole number clock frequency from 12Mhz and up. (For example it could work with a PCI interface's 66 Mhz clock)

Transceivers

Sital Technology's 1553 BC core connects to any standard transceiver-transformer pair. The core was fully validated with a 3rd party dual transceiver.

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