MIL-STD-1553 BC/RT/MT with PCI interface IP Core for FPGA
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MIL-STD-1553B Notice 2 Bus Controller, Remote Terminal, Bus monitor with PCI interafce IP Core for FPGA and ASIC Devices
The BRM1553PCI IP Core is suitable for any Mil-Std-1553 implementation. The core incorporates a backend logic that arranges the messages in a predefined memory structure, which simplifies the interface between the 1553 bus and the local CPU. The BRM1553PCI core can act as a full replacement (2nd source) for DDC® Micro-Ace® devices as the data is arranged in the same way and back-end interface is compatible to PCI.
Feature Summary:
- Mil-Std-1553 Intellectual Property for FPGAs and ASIC
- Suitable for any MIL-STD-1553 BC, RT, MT implementation
- Compatible to Enhanced DDC® Mini-Ace® interface and functionality, works with existing software drivers
- 33/66MHz PCI back-end interface
- Supports PCI Burst mode
- Small FPGA area utilization
- Up to 4 x 1553 cores with a single PCI interface
- Modular architecture allowing flexible implementations
- Provided with full verification environment
- Passed full RT validation testing by 3rd party
- Based on vendor and technology independent VHDL code
Back End Interface
Includes DDC’s® Micro-ACE® interface over PCI, compatible with existing drivers and applications.
- No need to rewrite drivers' code
- Eliminates replacement risk
PCI
The IP core includes a full PCI target interface.
- PCI specification 2.3 compliant
- 33MHz performance (66MHz optional)
- 32 bit datapath
- Zero wait states burst mode
- Full Target functionality
Gate Count
Sital’s BRM1553PCI requires very small space from FPGA for complex applications.
The following table shows examples of the area usage, in different FPGA devices:
| Vendor | Product Family | Area Usage (4-LUT count) | |
| BC+RT+MT | RT Only | ||
| Altera | Cyclone 3 | 4620 | 3550 |
| Xilinx | Spartan 3 | 4500 | 3360 |
| Lattice | XP2 | 4250 | 3100 |
| Xilinx, Altera | Older FPGA families | 5440 | 3700 |
* Other FPGA vendors and families are available
* Actual area usage may vary according to core configuration and FPGA.
Manchester Decoder
The unique Manchester decoder can work with any even clock frequency from 12Mhz and up to reduce clock
sources and clock domains on board (reduces EMI/RFI).
Advanced algorithms for filtering out noise and disturbances enable the core to operate in harsh environments.
Transceivers
Sital Technology's 1553 BC core connects to any standard transceiver-transformer pair. The core was fully validated with a 3rd party dual transceiver.
* DDC® and Micro-ACE® are registered trademarks of Data Device Corporation, Bohemia, NY, USA. There is not any affiliation between Data Device Corporation and Sital technology, Ltd.