MIL-STD-1553B Notice 2 Monitor Terminal front end Core for FPGA Devices
Feature Summary:
- MIL-STD-1553B Notice 2 Monitor Terminal (MT).
- Suitable for any MIL-STD-1553 Monitor Terminal implementation.
- CPU host interface not needed.
- Best gate count in the industry.
- Supports any whole number clock frequency.
- Connects to any transceiver-transformer pair.
- Full MIL-STD-1553 Validation test passed in 3rd party tester.
- Vendor and technology independent IEEE-1076 VHDL design and coding.
Back End Interface
The 1553 MT front-end core interfaces the backend with a simple address-data read and write "bus cycles".
When a message is intercepted, then the core checks a designated signal to decide wether to write the message into the memory or not.
This signal can be produced by software or by user's logic. For example - a user can build a decoder for a specific address to be monitored.
When monitoring a message, the core produces a write cycle. The user can build a FIFO mechanism or simple registers in his FPGA to interface this simplified backend interface.
This core is best used where CPU is not required.
The Monitor Terminal can operate either as a "Word monitor" - where words are tagged and recorded (used for example for a bus dump),
or as a "Message monitor" - where complete messages are monitored.
Each core actually consists of 2 monitors - one for each 1553 channel, thus always selecting the active message to be monitored.
Gate Count
| Vendor | Family | Used logic |
| Altera | Cyclone | 823 LEs |
| Altera | Stratix | 820 LEs |
| Xilinx | Spartan2E | 490 Slices |
| Xilinx | Virtex II | 487 Slices |
Manchester Decoder
The unique Manchester decoder can work with any whole number clock frequency
from 12Mhz and up. (For example it could work with a PCI interface's 66 Mhz clock)
Transceivers
Sital Technology's 1553 RT core connects to any standard transceiver-transformer pair.
The core was fully validated with a 3rd party dual transceiver.
RT Validation
Sital Technology's 1553 RT core has been successfully implemented in a 3rd party FPGA, and has passed the full MIL-STD-1553B Notice 2 RT Validation test plan in an independent laboratory.
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