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The future of 1553 is in IP cores. Click here to learn why.

MIL-STD-1553 RT, BC, MT Front End Intellectual Property Core

MIL-STD-1553B Notice 2 Remote Terminal, Bus Controller, Monitor front end Core for FPGA and ASIC Devices

The BC/RT/MT 1553FE IP Core is suitable for small and simple Mil-Std-1553 implementations, where no CPU is present or required or where relatively short messages are sent over the bus.
The core is particularly useful in obsolete replacement designs and simple applications.

Feature Summary:

Mil-Std-1553 Intellectual Property for FPGAs and ASIC
Suitable for any MIL-STD-1553 RT, BC, MT implementation
Very small FPGA area utilization
Supports any even clock frequency
Does not require CPU for management, no SW required
Modular architecture allowing flexible implementations
Provided with full verification environment
Passed full validation testing by 3rd party
Eliminates risks related to parts obsolescence
Based on vendor and technology independent VHDL code

Back End Interface

The BC/RT/MT 1553FE interfaces with the back-end through simple address-data read and write "bus cycles".

No CPU is required
Simple integration with user's logic

Gate Count

Sital's MIL-STD-1553 IP requires very small space from FPGA. The following table shows examples of the area usage, in different FPGA devices:

Vendor Family Area Usage (4-LUT count)

Altera Stratix, Cyclone 930

Xilinx Virtex-II, Spartan 3 805

Lattice LatticeXP 764

QuickLogic PolarPro 1059

Actel RTAX-S 1036 Modules

* These numbers are approximate.
* Other FPGA vendors and families are available
* Actual area usage may vary according to core configuration.

Manchester Decoder

TThe unique Manchester decoder can work with any even clock frequency from 12Mhz and up to reduce clock sources and clock domains on board (reduces EMI/RFI).
Advanced algorithms for filtering out noise and disturbances enable the core to operate in harsh environments.

Transceivers

Sital Technology's 1553 RT core connects to any standard transceiver-transformer pair. The core was fully validated with a 3rd party dual transceiver.

RT Validation

Sital Technology's 1553 RT core has been successfully implemented in a 3rd party FPGA, and has passed the full MIL-STD-1553B Notice 2 RT Validation test plan in an independent laboratory.

Download:

	Product Brochure
	Product Selection Guide
	White Paper: The Evolution of Mil-Std-1553 IP Cores